1. Field of the Invention
This invention generally relates to methods of performing reads and writes in computer systems, and, more specifically, relates to a method for minimizing the number of write cycles on a PCI bus when the bytes to be written are not contiguous.
2. Description of the Related Art
The applicable related art is a small computer system that has an Intel Pentium microprocessor and a local Peripheral Component Interconnect (PCI) bus for Input/Output (I/O) devices that have high bus bandwidth requirements. The operation of the PCI bus can be best understood by referring to PCI Local Bus Specification, Rev. 2.0 (PCI Special Interest Group, Apr. 10, 1993), which is incorporated herein by reference.
The Pentium microprocessor has a bus width of 64 bits, known as a quad word. The PCI bus, over which the Pentium microprocessor writes data to the high bus bandwidth I/O devices, has a width of 32 bits, known as a double word. A control device known as a Pentium-to-PCI bridge (Bridge) must therefore be provided to translate data from the quad word Pentium bus to the double word PCI bus.
The Pentium microprocessor always writes data to the Bridge in contiguous bytes. The Bridge provides an optional write buffer to allow the Bridge to store up to eight 64-bit quad words written from the Pentium processor. This write buffer allows the Bridge to perform the writes from the write buffer to the PCI bus as its timing allows, eliminating the need for complex circuitry to synchronize the operation of the Bridge exactly to the operation of the Pentium bus. When the write buffer option is enabled, writes by the Pentium processor are routed through the write buffer. To minimize the number of write cycles to the PCI bus, the Bridge has a combine feature which looks for data within the write buffer that is at the same quad word address. If the Bridge finds two writes to the same quad word address, it simply combines the data in the two quad word locations according to which bytes in these locations are valid. If some of the same bytes are enabled in the more recent location within the write buffer as are enabled in a later location, the data within the more recent location takes precedence and is written during the combined write cycle.
While the Pentium processor always writes data in contiguous bytes, the combine feature of the Bridge may create combined data which has non-contiguous bytes. For example, a Pentium write of byte 0 and a second Pentium write of byte 2 to the same quad word address would be combined into a single PCI bus write cycle of bytes 0 and 2. Some I/O devices coupled to the PCI bus may not, however, be able to handle PCI bus write cycles of non-contiguous bytes. This problem has been addressed in prior art devices by detecting writes with non-contiguous bytes, and generating as many PCI bus write cycles as there were non-contiguous bytes, For example, if the valid bytes were bytes 1, 3, 5, and 7, four separate PCI bus write cycles would be generated.
Therefore, there existed a need to provide a method for detecting a PCI bus write cycle of non-contiguous bytes, and to use the multiple data phase capability of the PCI bus to transfer these non-contiguous bytes in a maximum of two PCI bus write cycles.